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Choi, J. and Dornfeld, D. (2005), “Chip Scale Topography Evolution Model for CMP Process Optimization”, Proc. IEEE International Symposium on Semiconductor Manufacturing (ISSM), San Jose, CA, Sept 13-15, pp 430-433.

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ABSTRACT:
A new chip scale model integrating pad height distribution and it’s interaction with topography on a patterned wafer was tested. Pad asperity height distribution was used to calculate mean contact pressure at a single asperity contact region. Material removal by a single asperity was evaluated from Hertzian elastic contact model and abrasive indentation model. Simulation on a test pattern predicted relatively higher removal rate and lower planarization efficiency with higher nominal down pressure. Oxide thickness variation over a test chip for a time period measured from specially designed test structure matched well with the model prediction.

SUGGESTED CITATION:
Jihong Choi and David Dornfeld, "Chip Scale Topography Evolution Model for CMP Process Optimization" (September 1, 2005). Laboratory for Manufacturing and Sustainability. Precision Manufacturing Group. Paper choi_05_2.
http://repositories.cdlib.org/lma/pmg/choi_05_2